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An Adder-Free Method for a Small Size π/4 Shift QPSK Signal Generator
Akira YASUDA Hiroshi TANIMOTO Chikau TAKAHASHI Akira YAMAGUCHI Masayuki KOIZUMI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
analog circuits and signal processing, QPSK signal generator, delta-sigma modulator, intergrated electronics,
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A novel adder-free architecture for realizing a small-size π/4-shift QPSK signal generator IC is presented. In order to realize an adder function, analog current-mode addition is utilized instead of digital adders. Impulse responses of a roll-off filter are stored in a ROM as a Δ-Σ modulated one-bit data stream. This can greatly reduce the die size to 0.8mm 0.8mm while maintaining high modulation accuracy. The test chip was fabricated by using the standard 0.8µm CMOS technology, and the chip achieved 1.8% vector modulation error with a 2.7V power supply.