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DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses
Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Digital Signal Processing
digital signal processor, compiler, code optimization, memory addressing,
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Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.