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A Self-Synchronization Method for the SS-CSC System
Hiromasa HABUCHI Toshio TAKEBAYASHI Takaaki HASEGAWA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Spread Spectrum Techniques and Applications)
M-ary orthogonal system, bi-orthogonal system, self-synchronization, frame synchronization, differential detector, racing counters,
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In this paper, a simple frame synchronization method for the SS-CSC syytem is proposed, and the synchronization performance is analyzed. There have been growing interests in the M-ary/SS communication system and the bi-orthogonal modulation system because these systems can achieve the high frequency utilization efficiency. However, the frame synchronization is difficult. We proposed the SS-CSC system, and evaluated the bit error rate (BER) performance of the SS-CSC system under the completed synchronization. The BER performance of the SS-CSC system is much the same as that of the bi-orthogonal modulation system. In this paper, a frame synchronization method using the differential detector and racing counters is proposed. In particular, the lose lock time, the recovery time and the BER performance considering the synchronizing performance are analyzed. In consequence, the BER performance considering the synchronization performance can approach the lower bound of the SS-CSC system by tuning the number of the stages in racing counters.