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PatternBased Maximal Power Estimation for VLSI Chip Design
WangJin CHEN WuShiung FENG
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E80A
No.11
pp.23002307 Publication Date: 1997/11/25 Online ISSN:
DOI: Print ISSN: 09168508 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: maximal power dissipation, simulated annealing, walk through, power estimation, power optimization,
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Summary:
In recently year, the analysis of power management becomes more important. It is difficult to obtain the maximum power because this is NPcomplete. For an ninput circuit, there are 2^{2n} different input patterns to be considered. There are two major methods for this problem. First method is to generate input patterns to obtain the maximal power by simulating these generated patterns. This method is called pattern based. The other one uses probability method to estimate the power density of each node of a circuit to calculate the maximal power. In this paper, we use a pattern based method to estimate the maximal power. This method is better than that of probability for the simulation of power activity. In practical applications, these generated patterns can be applied and observe the activity of a circuit. These simulated data can be used to examined the critical paths for performance optimization. A simulated annealing algorithm is proposed to search input patterns for maximum power. Firstly, it transforms this problem into an optimization problem to adapt the simulated annealing method. In this method, there are three strategies for generating the next input patterns, called neighborhood. In the first strategy, it generates the next input pattern by changing the status of all input nodes. In the second strategy, some input nodes are selected and changed randomly.

