Architecture Evaluation Based on the Datapath Structure and Parallel Constraint

Masayuki YAMAGUCHI  Akihisa YAMADA  Toshihiro NAKAOKA  Takashi KAMBE  Nagisa ISHIURA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E80-A   No.10   pp.1853-1860
Publication Date: 1997/10/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance evaluation,  datapath,  structure,  parallel constraint,  

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Summary: 
This paper presents a novel way of evaluating architecture of embedded custom DSPs which helps designers optimizing the datapath configuration and the instruction set. Given a datapath structure, it evaluates the performance in terms of the estimated number of steps to execute the target program on the datapath. A concept of "parallel constraint" is newly introduced, which enables evaluation of the impact of instruction format design on the performance without explicity specifying the instruction format. The number of execution steps is estimated by a combination of static analysis and dynamic analysis. It enables fast and precise estimation of actual performance in the early design stage. We have developed an architecture evaluation system based on the presented method and applied it to some actual design of signal processors. We demonstrate the accuracy of estimation and the usefulness of the method through its applications.