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Top-Down Co-simulation of Hardware/Software Co-designs for Embedded Systems Based Upon a Component Logical Bus Architecture
Katsuhiko SEO Hisao KOIZUMI Barry SHACKLEFORD Mitsuhiro YASUDA Masashi MORI Fumio SUZUKI
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
co-design, co-simulation, embedded system, component logical bus,
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We propose a top-down approach for cosimulation of hardware/software co-designs for embedded systems and introduce a component logical bus architecture as an interface between software components implemented by processors and hardware components implemented by custom logic circuits. Co-simulation using a component logical bus architecture is possible is the same environment from the stage at which the processor is not yet finalized to the stage at which the processor is modeled in register transfer language. Models based upon a component logical bus architecture can be circulated and reused. We further describe experimental results of our approach.