A Supplementary Scheme for Reducing Cache Access Time

Jong-Hong BAE  Chong-Min KYUNG  

IEICE TRANSACTIONS on Information and Systems   Vol.E79-D   No.4   pp.385-387
Publication Date: 1996/04/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: LETTER
Category: Computer Hardware and Design
computer architecture,  cache,  penalty cycles,  pipeline,  

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Among three factors mainly affecting the cache access time, i. e., hit access time, miss rate and miss penalty, previous approaches were focused on reducing the hit access time and miss rate. In this paper, we propose a scheme called MPC (Miss-Predicting Cache) which achives additional reduction of the average instruction cache access time through reducing the miss penalty. The MPC scheme which predicts cache miss and starts cache miss operations in advance, therefore, is supplementary to previous cache schemes targeted for reducing the miss rate and/or hit access time. Performance of the MPC scheme was evaluated using dinero, a trace-driven cache simulator, with the estimation of silicon area using 0.8 µm CMOS standard cell library.