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Floating Point Adder/Subtractor Performing IEEE Rounding and Addition/Subtraction in Parallel
Woo-Chan PARK Shi-Wha LEE Oh-Young KWON Tack-Don HAN Shin-Dug KIM
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Hardware and Design
FPU (Floating Point Unit), floating point adder/subtractor, IEEE rounding, carry select adder,
Full Text: PDF(802.8KB)>>
A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.