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A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
design for testability, partial scan design, register-transfer level, automatic test-pattern generation, ESDA,
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An approach to design for testability using register-transfer level (RTL) partial scan selection is described. We define an RTL circuit model which enables efficient description in an electronic system design automation (ESDA) tool and testability analysis which leads to effective partial scan selection for RTL design including data path circuits and control circuits such as state machines. We also introduced a method of partial scan selection at RTL which selects critical registers and state machines based on RTL testability analysis. DFT techniques using gate level testability measures have been studied and concluded that they are not successful in achieving high fault coverage . However, we started this work for the following reasons, 1) In sequential ATPG procedure, more than two memory elements belonging to a functional units such as registers and state machines are often required to be justified at a time. At RTL, state machines and registers are explicitly described and recognized as functional units while gate level memory elements are scattered over the circuit. 2) As discussed in , if the circuit is modified so that the test sequence which causes state transition between initial and final states of sequential ATPG can be easily obtained, ATPG results can be also improved. Complex state machines can be identified at RTL. According to the experimental results, our gate level DFT achieves high fault coverage comparable with the previously published most successful DFT methods, and DFT at RTL resulted in higher fault coverage than gate level DFT at much shorter CPU time.