ASYL-SdF: A Synthesis Tool for Dependability in Controllers

Raphael ROCHET  Regis LEVEUGLE  Gabriele SAUCIER  

IEICE TRANSACTIONS on Information and Systems   Vol.E79-D   No.10   pp.1382-1388
Publication Date: 1996/10/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
synthesis tool,  finite state machines,  dependability,  fault detection,  fault tolerance,  

Full Text: PDF>>
Buy this Article

Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.