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Regenerative Pass-Transistor Logic: A Circuit Technique for High Speed Digital Design
Tsz Shing CHEUNG Kunihiro ASADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/09/25
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
pass-transistor logic, dual-rail logic, Monte Carlo method, logic gates, arithmetic logic design,
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Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was developed. The technique can be applied to basic logic gates, full adders, multiplier units, and more complicated arithmetic logics like Conditional Carry Select (CCS) circuit. The magnitude of propagation delay time of RPL is smaller than the conventional CPL(Complementary Pass-transistor Logic), or DPL (Double Pass-transistor Logic). Low power consumption can also be achieved by reduced number of transistors and metal interconnections. Simulation and layout data also proved that RPL is advantageous over existing dual-rail logics while considering speed, power consumption and layout area.