IEICE Trans - SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories

SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories

Shigehiro KUGE
Fukashi MORISHITA
Takahiro TSURUDA
Shigeki TOMISHIMA
Masaki TSUKUDE
Tadato YAMAGATA
Kazutami ARIMOTO

Publication
IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.997-1002
Publication Date: 1996/07/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory
Keyword:

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Summary:
This parer describes a silicon on insulator(SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline Short is also discussed in respect of yield and area penalty.