Publication IEICE TRANSACTIONS on ElectronicsVol.E79-CNo.7pp.978-985 Publication Date: 1996/07/25 Online ISSN: DOI: Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996)) Category: Memory Keyword:
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Summary: This paper descriles a 256 Mb DRAM chip architecture which provides up to 32 wide organization. In order to minimize the die sixe, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25µmCMOS technology. The chip measures 13.25mm21.55mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe(RAS) access time of 26 ns was obtained under 2.8 V power supply and 85 . In addition, a 100 MHz32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output(EDO) cycle has been succssfully demonstrated.