Fault-Tolerant Designs for 256 Mb DRAM

Toshiaki KIRIHATA  Yohji WATANABE  Hing WONG  John K. DEBROSSE  Munehiro YOSHIDA  Daisuke KATO  Shuso FUJII  Matthew R. WORDEMAN  Peter POECHMUELLER  Stephen A. PARKE  Yoshiaki ASAO  

IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.7   pp.969-977
Publication Date: 1996/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory

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This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm2 256 Mb DRAM with 32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's(MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occursas a result of a wordlinebitline short-circuit to only 15 µA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intrablock/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield.