A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU

Katsumi DOSAKA  Akira YAMAZAKI  Naoya WATANABE  Hideaki ABE  Jun OHTANI  Toshiyuki OGAWA  Kazunori ISHIHARA  Masaki KUMANOYA  

IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.7    pp.948-956
Publication Date: 1996/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Memory

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This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. And fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-µm CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3mm2 is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-hit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants(PDA's), personal computer systems, and embedded controller applications.