Capacitance Coupling Immune, Transient Sensitive Accelerator for Resistive Interconnect Signals of Subquarter Micron ULSI

Tomofumi IIMA
Masayuki MIZUNO
Tadahiko HORIUCHI
Masakazu YAMASHINA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.7    pp.942-947
Publication Date: 1996/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Interface Circuits
Keyword: 


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Summary: 
This paper presents a new circuit scheme called a transient sensitive accelerator(TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively, A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.