An 80-MOPS-Peak High-Speed and Low-Power-Consumption 16-b Digital Signal Processor

Hideyuki KABUO  Minoru OKAMOTO  Isao TANAKA  Hiroyuki YASOSHIMA  Shinichi MARUI  Masayuki YAMASAKI  Toshio SUGIMURA  Katsuhiko UEDA  Toshihiro ISHIKAWA  Hidetoshi SUZUKI  Ryuichi ASAHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.7   pp.905-914
Publication Date: 1996/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
Category: Logic
Keyword: 


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Summary: 
This paper describes a 16-b fixed point digital signal processor(DSP), especially its multiply-accumulate(MAC) unit, memories, and instruction set.By adopting a redundant binary multiplier and a variable pipeline structure, this DSP's MAC unit, compared to a conventional MAC unit, consumes about 15% less power and operates 24% faster. Furthermore, its doublespeed MAC mechanism can realize twice the performance of a single MAC operation while consuming only 69% more power. By being able to more finely control which portions of memory are activated, the data ROM and data RAM's precharge current was reduced to about 1/8 of the conventional ROM and RAM's. We redesigned the instruction set and reduced its width from 32 b to 24 b based on the analysis of data generated by simulating an application program on our previous DSP. The reduction in instruction width made our on-chip instruction memory size 33% smaller than the previous one. This chip is fabricated with a 0.5- µm double-metal-layer CMOS process and achieves 80-MOPS-peak double speed multiply-accumulate performance.