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A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture
Satoru TANOI Tetsuya TANABE Kazuhiko TAKAHASHI Sanpei MIYAMOTO Masaru UESUGI
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/07/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))
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A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (Dll) for deskew, and a frequency-locked loop(FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector newly developed which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4µm CMOS technology is used to fabricate the chip.