A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories

Hiroshi NAKAMURA
Jun-ichi MIYAMOTO
Ken-ichi IMAMIYA
Yoshihisa IWATA
Yoshihisa SUGIURA
Hideko OODAIRA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.6    pp.836-844
Publication Date: 1996/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memory,  sense amplifier,  bit-by-bit program verify,  capacitive coupling,  page copy,  

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Summary: 
This paper describes a newly developed sensing scheme with a bit-by-bit program verify technique for NAND flash disk systems. This sensing scheme achieves good noise immunity for large capacitive coupling between bitlines, and makes NAND flash memories operable for flexible power supply voltages including both 3.3V and 5V. A highly reliable read operation is performed for power supply voltages above 3V and a bitline-bitline coupling ratio below 50%. The sensing scheme also achieves an intelligent page copy function with 20% reduction in time and without external buffers and CPU resources.