2V/120 ns Embedded Flash EEPROM Circuit Technology

Horoshige HIRANO  Toshiyuki HONDA  Shigeo CHAYA  Takahiro FUKUMOTO  Tatsumi SUMI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.6   pp.825-831
Publication Date: 1996/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memory,  low voltage operation,  erase algorithm,  boost circuit,  

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Summary: 
A 2V/120 ns flash EEPROM embedded in a microcontroller has been fabricated in 0.8 µm double-metal CMOS process technology with a simple stacked gate memory cell. To achieve low voltage and high speed operation, novel circuit technology and architecture; (a) PMOS-precharging NMOS-self-boost word line circuit with a higher voltage selector, (b) new erase algorithm for reverse operation, (c) column gate boost circuit, (d) hard-verify mode for replacing weak cells, (e) efficient redundancy of row and column lines, have been developed. A 512 kb flash EEPROM core chip incorporating these circuit techniques and architecture operate at 1.8 V and accesses data in 120 ns at 2 V and 70.