NAND-Structured DRAM Cell with Lithography-Oriented Design

Masami AOKI
Tohru OZAKI
Takashi YAMADA
Takeshi HAMAMOTO

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.6    pp.792-797
Publication Date: 1996/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memory,  DRAM,  stacked capacitor,  

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Summary: 
A 0.96µm2 NAND-structured stacked capacitor cell has been achieved using conventional i-line photolithography and a 0.4µm design rule. Memory cell patterns for critical levels have been designed with a simple lineand-space configuration and a completely repeated hole arrangement for large lithography process margin. The word-line pitch and bit-line pitch are 0.9µm and0.95µm, respectively. In order to obtain sufficient storage capacitance and large alignment margin, a self-aligned cylindrical stacked capacitor and bit line plug fabrication process has been developed. These new technologies have enabled storage capacitance of 15 fF/cell with a 0.5µm capacitor height and a 5 nm equivalent SiO2 film thickness for nitride-top oxide(NO) film in the bit-line over capacitor(BOC) structure. Due to its lithography-oriented cell design and self-aligned process procedure, the present cell is a promising candidate for 256 Mb DRAM and beyond.