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A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
memory, DRAM, hierarchical bit-line, refresh,
Full Text: PDF(494.5KB)>>
A crossing charge recycle refresh(CCRR) scheme and a serial charge recycle refresh(SCRR) scheme are proposed for the large capacity DRAMs with hierarchical bit-line architecture to reduce main bit-line charging current. A separated driver sense-amplifier(SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense-amplifiers. These circuits are applied to an experimental 1-Gb DRAM, which achieves reduction of main bit-line charging current to 37.5%.