A 5 ns Cycle 1 Mb Synchronous SRAM with a Fast Write Technology

Sadayuki OHKUMA  Hiroshi ICHIKAWA  Seigo YUKUTAKE  Hitoshi ENDO  Shuichi KUBOUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.6   pp.763-766
Publication Date: 1996/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
synchronous SRAM,  late write,  short cycle time,  regisler,  

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Summary: 
A GTL/LV-CMOS interfaced 1 M bit(32k words 36bits/64k words18bits) BiCMOS cache SRAM is designed within a 5.65 10.54mm2 chip size. The process is 0.4µm BiCMOS with 4 poly-Si layers, 3 Metal layers, and TFT memory cells(2.66 4.94µm2). The late write operation is newly adopted. The late write operation method improvements make the fast access time 6 ns and the shorter cycle time 5 ns.