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Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment
Hiroyuki HARA Masataka MATSUI Goichi OTOMO Katsuhiro SETA Takayasu SAKURAI
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
MPEG2 decoder LSI, compression/decompression, orthogonal memory, embedded memory, on-chip memory testability,
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Special memory and embedded memories used in a newly designed MPEG2 decorder LSI are described. Orthogonal memory, which has a functionality of parallel-to-serial transposition, is employed in a IDCT(Inverse Discrete Cosine Transform) block for small area and low-power. The orthogonal memory realizes the special pupose with 50% of the area and the power compared with using flip-flop array. FIFO's and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. Flip-Flop cell is one of the important memory elements in the MPEG environment, and is also improved for the low-cost optimizing functionality for video processing. The area and power of the fabricated MPEG2 decoder chip are reduced by 20% using these techniques. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder LSI are also described.