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A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
integrated electronics, high density SRAM, hierarchical bit line organization, T-shaged bit line,
Full Text: PDF(796.2KB)>>
This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.