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111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
memory, synchronous SRAM, high speed SRAM, low power, clock,
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This paper reports a 32k32 1-Mbit CMOS synchronous pipelined burst SRMA. A clock access time of 3.6 ns and a minimum cycle time of 9 ns(111 MHz operation) were obtained. An active current of 210 mA at 111 MHz and a standby current of 2 µA were successfully realized. These results can be obtained by a new activation control method in which the internal clock pulses control the decoders, the low resistive bit line and memory cell GND line and the optimization of write recovery timing and data sense timing.