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A 2.6-ns 64-b Fast and Small CMOS Adder
Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
addition, carry look-ahead adder, binary look-ahead adder, carry select, modified carry select, CMOS, VLSI,
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We present a 64-b adder having a 2.6-ns delay time at 3.3 V power supply within 0.27 mm2 using 0.5-µm CMOS technology. We derived our adder design from architectural level considerations. The considerations include not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. As a result, a 64-b adder, (56-b Carry Look-ahead Adder(CLA) +8-b Carry Select Adder (CSA)), was designed. In this design, a new carry select scheme called Modified Carry Select (MCS) is also proposed.