Trends in High-Speed DRAM Architectures

Masaki KUMANOYA  Toshiyuki OGAWA  Yasuhiro KONISHI  Katsumi DOSAKA  Kazuhiro SHIMOTORI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.4   pp.472-481
Publication Date: 1996/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
review,  DRAM,  high-speed DRAM,  main memory,  graphics memory,  performance gap,  bandwidth bottleneck,  performance comparison,  high-speed I/O interface,  unified memory,  system integration,  

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Summary: 
Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.