A New Hierarchical RSM for TCAD-Based Device Design in 0.4µm CMOS Development

Hisako SATO  Katsumi TSUNENO  Kimiko AOYAMA  Takahide NAKAMURA  Hisaaki KUNITOMO  Hiroo MASUDA  

IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.2    pp.226-233
Publication Date: 1996/02/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Statistical Analysis
TCAD,  RSM,  CMOS design,  

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A new methodology for simulation-based CMOS process design has been proposed, using a Hierarchical Response Surface Method (HRSM) and an efficient experimental calibration. The design methodology has been verified using a 0.4 micron CMOS process. The proposed HRSM achieved a 60% reduction of process and device design cost in comparison with those of conventional TCAD. The procedure was performed in conjunction with an experimental calibration technique to provide a reliable threshold voltage prediction including process variation effects. The total CPU cost was 200 hr. on SUN SPARC 10 and the error of the predicted threshold voltage was less than 0.02 V.