The Application of DOE and RSM Techniques for Wafer Mapping in IC Technology

Anthony J. WALTON  Martin FALLON  David WILSON  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C    No.2    pp.219-225
Publication Date: 1996/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Statistical Analysis
Keyword: 
DOE,  RSM,  wafer mapping,  test structures,  integrated circuits,  

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Summary: 
The objective, when mapping a wafer, is to capture the the full variation across the wafer while minimising the number of measurements. This is a very similar objective to that of experimental design and this paper applies classical Design Of Experiment (DOE) techniques to the selection of measurement points for wafer mapping. The resulting measurements are then fitted using Response Surface Methodology (RSM) from which contour plots or wafer maps can be generated. The accuracy of the fit can be ascertained by inspection of the adjusted R2 value and it is demonstrated that in many cases transformations can be used to improve the accuracy of the resulting wafer maps.