For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrodes in Wafer Processing
Hiroki KUBO Takashi NAMURA Kenji YONEDA Hiroshi OHISHI Yoshihiro TODOKORO
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Reliability Analysis
antenna capacitor, charge build-up, charge to breakdown, ion implantation,
Full Text: PDF(782.5KB)>>
A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.