Evaluation of Soft-Error Immunity for 1-V CMOS Memory Cells with MTCMOS Technology

Takakuni DOUSEKI  Shin'ichiro MUTOH  Takemi UEKI  Junzo YAMADA  

IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.2   pp.179-184
Publication Date: 1996/02/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
soft-error,  1-volt,  multi-threshold,  CMOS,  memory,  

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Soft-error immunity of a 1-V operating CMOS memory cell is described. To evaluate the immunity precisely at the supply voltage of 1 V, a multi-threshold CMOS (MTCMOS) memory scheme, which has a peripheral circuit combining low-threshold CMOS logic gates and high-threshold MOSFETs with a virtual supply line, is adopted as a test structure. A 1-kb memory was designed and fabricated with 0.5-µm MTCMOS technology and the soft-error immunity of the memory cells was evaluated. The results of an alpha-particle exposure test and a pulse laser test show that a full-CMOS memory cell has high immunity at 1-V operations.