Design Methodology of Deep Submicron CMOS Devices for 1 V Operation

Hisato OYAMATSU  Masaaki KINUGAWA  Masakazu KAKUMU  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E79-C   No.12   pp.1720-1725
Publication Date: 1996/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
low voltage,  low power dissipation,  threshold voltage,  CMOS,  

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Summary: 
A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.