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Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells
Toru IWATA Hiroyuki YAMAUCHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)
DRAM, data retention, memory-cell leakage current,
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To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.