Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions

Hideaki YAMANAKA  Hirotaka SAITO  Hirotoshi YAMADA  Harufusa KONDOH  Hiromi NOTANI  Yoshio MATSUDA  Kazuyoshi OSHIMA  

Publication
IEICE TRANSACTIONS on Communications   Vol.E79-B   No.8   pp.1109-1120
Publication Date: 1996/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Switching and Communication Processing
Keyword: 
ATM switch architecture,  hierarchical queueing,  multicast functions,  ATM access systems,  ATM loop systems,  

Full Text: PDF>>
Buy this Article



Summary: 
A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.