IEICE Trans - VLSI-Oriented Input and Output Buffered Switch Architecture for High-Speed ATM Backbone Nodes

VLSI-Oriented Input and Output Buffered Switch Architecture for High-Speed ATM Backbone Nodes

Yukio KAMATANI  Yoshihiro OHBA  Yoshimitsu SHIMOJO  Koutarou ISE  Masahiko MOTOYAMA  Toshitada SAITO

Publication
IEICE TRANSACTIONS on Communications   Vol.E79-B    No.5    pp.647-657
Publication Date: 1996/05/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on High Speed Local Area Network)
Category:
Keyword:
ATM,  switch,  node,  high-speed,  backbone,  flow control,  input buffer,  output buffer,  shared buffer,  multicast,  QoS,  LSI,

Full Text: PDF(950.5KB)>>

Summary:
Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10Gbps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.