Integrated Switching Architecture and Its Traffic Handling Capacity in Data Communication Networks

Noriharu MIYAHO

IEICE TRANSACTIONS on Communications   Vol.E79-B    No.12    pp.1887-1899
Publication Date: 1996/12/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Communication Systems and Transmission Equipment
packet switching,  circuit switching,  ATM,  hierarchical memory system,  random time-slot,  CAM,  

Full Text: PDF>>
Buy this Article

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.