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Parallel Encoder and Decoder Architecture for Cyclic Codes
Tomoko K. MATSUSHIMA Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E79A
No.9
pp.13131323 Publication Date: 1996/09/25
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: error correction, cyclic code, parallel architecture, circuit design, encoder, decoder,
Full Text: PDF(772.7KB)>>
Summary:
Recently, the highspeed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of highspeed error correction circuits. Parallel processing has been found to be an effective method of speeding up operarions, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows H symbols to be processed in parallel, where H is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols H. As an example, we investigate hardware complexity for a ReedSolomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H, the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that a parallel ReedSolomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

