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Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL
Takao ONOYE Gen FUJITA Masamichi TAKATSU Isao SHIRAKAWA Nariyoshi YAMAI
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E79-A
No.8
pp.1210-1216 Publication Date: 1996/08/25
Online ISSN:
DOI:
Print ISSN: 0916-8508 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: MPEG2, HDTV, VLSI, motion estimation,
Full Text: PDF>>
Summary:
A single chip motion estimator is described dedicatedly for MPEG2 MP@HL moving pictures. Adopting a two-level hierarchical searching algorithm in detecting motion vectors, the computational labor can be reduced by 1/70 in comparison with the conventional algorithm. A novel mechanism is introduced into the full-search procedure, which attempts the maximum possible reuse of reference pixels in order to reduce the bandwidth of the frame memory interface. The proposed motion estimator is integrated in a 0.6 µm triple-metal CMOS chip, which contains 1,450 K transistors on a 12.7 13.7 mm2 die. The input clock rate can be attained up to 133 MHz, which enables the real time motion estimation for MPEG2 MP@HL.
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