A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code

Kazumasa KOBAYASHI  Kouji YAMANO  Hideki KOKUBUN  Kiichi KOBAYASHI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E79-A   No.7   pp.1060-1067
Publication Date: 1996/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
difference-set cyclic codes,  (1057,813) code,  majority logic decoding,  pipelining,  

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Summary: 
A new high-speed decoding algorithm for Difference-set cyclic codes, and the design and implementation of a 50 MHz CMOS LSI for decoding the (1057, 813) DSCC, are presented. The algorithm, called modified threshold decoding, makes it possible to introduce an arbitrary number of pipeline stages into feedback loops in decoding circuits. A prototype LSI containing about 13k logic gates was fabricated using 1 µm CMOS gate-array technology. The power consumption is less than 750 mW at a 50 MHz clock rate. It is available for digital data transmission systems having an I/O data rate of up to 25 MBPS. It is being used in experimental set-ups targeted at future digital broadcasting systems. The proposed algorithm has an important advantage for much longer codes as it has the potential to be used in the high-speed decoding of DSCCs having a code length longer than 1057.