1: n2 MOS Cascode Circuits and Their Applications

Koichi TANNO
Okihiko ISHIZUKA
Zheng TANG

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E79-A    No.12    pp.2159-2165
Publication Date: 1996/12/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: Analog Signal Processing
Keyword: 
MOS analog circuit,  MOS LSI,  circuit theory and design,  integrated circuit,  threshold voltage,  

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Summary: 
This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.