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1: n^{2} MOS Cascode Circuits and Their Applications
Koichi TANNO Okihiko ISHIZUKA Zheng TANG
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E79A
No.12
pp.21592165 Publication Date: 1996/12/25
Online ISSN:
DOI:
Print ISSN: 09168508 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: MOS analog circuit, MOS LSI, circuit theory and design, integrated circuit, threshold voltage,
Full Text: PDF>>
Summary:
This paper describes an Ntype and a Ptype MOS cascode circuit based on the squarelaw characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n^{2} for the Ntype MOS cascode circuit and n^{2}: 1 for the Ptype MOS cascode circuit. The N and Ptype MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the inputoutput relations of each type circuit. The secondorder effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a V_{T} level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and Ptype MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

