PCHECK: A Delay Analysis Tool for High Performance LSI Design

Yoshio MIKI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E79-A   No.12   pp.2117-2122
Publication Date: 1996/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
delay analysis,  critical path,  device delay,  wire delay,  PCHECK,  

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This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.