Synchronization Method Using Several Synchronizing Chips for M-ary/SS Communication System

Kouji OHUCHI  Hiromasa HABUCHI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E79-A   No.12   pp.1988-1993
Publication Date: 1996/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Secton on Spread Spectrum Techniques and Applications)
spread spectrum communication system,  M-ary/SS communication system,  frame synchronization system,  framing chips,  racing counters,  

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In this paper, a simple frame synchronization system for M-ary/SS communication systems is proposed, and synchronization performance and the resulting bit error rate performance are analyzed. The frame synchronization system uses racing counters and framing chips which are added to spreading sequences. M-ary/SS communication systems can improve bit error rate performance under the condition in which there is an additive white gaussian noise. Synchronization of M-ary/SS communication systems is difficult, however, because M-ary/SS communication systems have several spreading sequences. The authors proposed the simple frame synchronization system which uses only one chip in the spreading sequence as a framing signal. This system needs a long time for initial acquisition as the frame length is longer. The proposed system in this paper can make initial acquisition time short by increasing the number of framing chips. The proposed system corresponds to the conventional system when the number of framing chips is l. As the result, it is shown that several framing chips contribute to decrease the initial acquisition time. Moreover, the frame synchronization system can be applied to asynchronous M-ary/SSMA system when different framing chip pattern is assigned to each user.