A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects

Xiangqiu YU  Hiroshi TAKAHASHI  Yuzo TAKAMATSU  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E78-D   No.7   pp.822-829
Publication Date: 1995/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generation,  combinational circuits,  redundant faults,  delay effect,  extended seven-valued calculus,  

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Summary: 
Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.