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Register-Transfer Module Selection for Sub-Micron ASIC Design
Vasily G. MOSHNYAGA Yutaka MORI Keikichi TAMARU
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
module selection, register-transfer synthesis,
Full Text: PDF(358.9KB)>>
In order to shorten the time-to-market, Application-Specific Integrated Circuits (ASIC's) are designed from a library of pre-defined layout implementations for register-transfer modules such as multipliers, adders, RAM, ROM, etc. Current approaches to selecting the implementations from the library usually deal with their timing-area estimates and do not consider delay of the intermodule wiring. However, as sub-micron design rules are utilized for IC fabrication, wiring delay becomes comparable to the functional unit delay and can not longer be ignored even in register-transfer synthesis. In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC performance. The algorithm not only efficiently exploits multiple module realizations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on several benchmarks show that considering both module and wiring issues, more than 30% reduction of the total circuit delay can be achieved.