Test Synthesis from Behavioral Description Based on Data Transfer Analysis

Mitsuteru YUKISHITA  Kiyoshi OGURI  Tsukasa KAWAOKA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E78-D   No.3   pp.248-251
Publication Date: 1995/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
computer hardware and design,  hardware description language,  test synthesis,  SFL,  

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Summary: 
We developed a new test-synthesis that operates method based on data transfer analysis at the language level. Using this method, an efficient scan path is inserted to generate test data for the sequential circuit by using only a test generation tool for the combinatorial circuit. We have applied this method successfully to the behavior, logic, and test design of a 32-bit, RISC-type processor. The size of the synthesized circuit without test synthesis is 23,407 gates; the size with test synthesis is 24,811 gates. This is an increase of only a little over 6%.