Design of a Novel MOS VT Extractor Circuit

Koichi TANNO  Okihiko ISHIZUKA  Zhen TANG  

IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.9   pp.1306-1310
Publication Date: 1995/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
MOS analog circuit,  threshold voltage,  MOS LSI,  circuit theory and design,  integrated circuit,  

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This paper describes a novel input-free MOS VT extractor circuit. The circuit consists of a bias voltage block and a novel VT extractor block. The proposed VT extractor block has the advantages of the ground-referenced output, low influence of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's or Wang's.