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A 15-Gbit/s Si-Bipolar Gate Array
Ryuusuke KAWANO Minoru TOGASHI Chikara YAMAGUCHI Yoshiji KOBAYASHI Masao SUZUKI
IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed Electron Devices)
decision circuit, 4 : 1 multiplexer, temperature-compensated output buffer, SST-1C,
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We have developed a 15-Gbit/s 96-gate Si-bipolar gate array using 0.5-µm Si-bipolar technology, a sophisticated internal cell design, an I/O buffer design suitable for high-speed operation and high-frequency package technology. The decision circuit and 4 : 1 multiplexer fabricated on the gate array operate up to 15-Gbit/s and above 10-Gbit/s respectively. The data input sensitivity and the phase margin of the decision circuit are 53 mVpp and 288 at 10-Gbit/s operation. This gate array promises to be useful in shortening the development period and lowering cost of 10-Gbit/s class IC's.