IEICE Trans - Low Power Dissipation GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSIs

Low Power Dissipation GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSIs

Norio HIGASHISAKA
Masaaki SHIMADA
Akira OHTA
Kenji HOSOGI
Kazuo KUBO
Noriyuki TANINO

Publication
IEICE TRANSACTIONS on Electronics Vol.E78-C No.9 pp.1195-1202
Publication Date: 1995/09/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category:
Keyword:
MUX, DEMUX, GaAs, 2.5 Gbps, power,

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Summary:
In order to establish design and measurement technologies for an LSI that features high speed operation and low power dissipation, GaAs 2.5 Gbps 16 bit MUX/DEMUX LSIs have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. For the purpose of achieving stable operation against the transistor parameter deviation, a timing design called clock tracking is employed. Moreover, to ensure accurate performance measurement, a new measurement system is introduced. The measurement system consists of an error rate detector (ERD), a pulse pattern generator (PPG) and a high speed tester (HST). The performances tested by the measurement system show the power consumptions of MUX and DEMUX LSIs are 1.35 W and 0.95 W. Input phase margin of DEMUX LSI is 290 degrees at 2.5 Gbps operation. The technologies obtained through development of these MUX/DEMUX LSIs are applicable to other high speed and low power LSIs.