High Speed GaAs Digital Integrated Circuits

Masahiro AKIYAMA  Seiji NISHI  Yasushi KAWAKAMI  

IEICE TRANSACTIONS on Electronics   Vol.E78-C   No.9   pp.1165-1170
Publication Date: 1995/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices)
GaAs digital IC,  DCFL,  SBFL,  high speed,  low power,  self-alignment process,  recessed gate process,  circuit design,  standard cell,  

Full Text: PDF>>
Buy this Article

High speed GaAs ICs (Integrated Circutis) using FETs (Field Effect Transistors) are reported. As the fabricating techniques, ion implantation processes for both 0.5 µm and 0.2 µm gate FETs using W/Al refractory metal and 0.2 µm recessed gate process with MBE grown epitaxial wafers are shown. These fabrication processes are selected depending on the circuit speed and the integration level. The outline of the circuit design and the examples of ICs, which are developed for 10 Gb/s optical communication systems, are also shown with the obtained characteristics.